The present invention is directed to a communication system having terminal equipment connected via line terminal groups as well as a switching matrix network for through-connection of calls and having a multiprocessor system for central control.
During the course of developing more and more complex data processing systems/communication systems, prior art single processing systems were expanded into multiprocessor systems. In contrast to the single processor systems wherein data/status messages are sequentially processed, parallel processing is utilized in multiprocessor systems. Compared to single processor systems, the multiprocessor systems have significant advantages, as indicated, for example, by the great increase in processing speed. The parallel processing of a plurality of tasks is achieved in that a task to be processed is divided into a plurality of sub-tasks, whereby one microprocessor processes respectively one sub-task, and the sub-results are subsequently combined to form an overall result. The sub-tasks are handled on the basis of the processes sequencing at the individual processors. A task/sub-task can thereby be composed of different functional organization sequences in the system. Thus, one process sequencing on a processor handles tasks/sub-tasks of, for example, error correction procedures, time-monitoring procedures or procedures of switching technology. Two or more processes, however, cannot simultaneously handle a sub-task. This is controlled by a monitoring process in the operating system.
What is problematical, however, is that various processes simultaneously access a memory register and can thereby produce undefined conditions. European Patent Application 0 274 715 A3 discloses a method for preventing simultaneous access of two processes to a memory register. By entering a processor number into the appertaining memory registers, the disclosed SECURE procedure prevents simultaneous access of a first process and of a competing, second process to this memory register. This occurs in that the competing, second process only modifies the memory contents of a memory register when a processor number is entered therein. Otherwise, this corresponds to the momentary access of an earlier, first process to that memory register and the competing, second process is entered into a waiting queue behind the first process. As soon as the present access is ended, the competing, second process in the waiting queue is now allowed to access this memory register. A simultaneous access of two processes to a memory register is thus prevented.
In a communication system, all processes are subjected to a hierarchic organizational structure. This is achieved by a prioritization of the process sequence. Thus, for example, a process having a higher priority can interrupt a process having lower priority at any time. When the process with higher priority has ended its task, a process having a lower priority can continue the handling of its original task. In communication systems, such processes having high priority are usually processes for error correction, time monitoring, etc. This, however, means that a process handling a task can be noticeably retarded in terms of its chronological sequence by a process having a higher priority. This is a particular disadvantage in that the sequence of the sub-tasks must be strictly adhered to.
Such a situation is to be avoided under all circumstances. When this situation occurs, the communication system therefore aborts the corresponding connection. One possibility of alleviating this situation is in employing known acknowledgement methods (such as handshaking). These methods can in fact be employed for data processing systems since the user (programmer) can wait a few 100 milliseconds in the least favorable case. In modern communication systems, however, the employment of such methods would lead to such a great load on the central bus system, as well as, on the corresponding processors that the resulting chronological delays could no longer be tolerated.